This application claims the priority of Korean Patent Application No. 2003-9808, filed on Feb. 17, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an address buffer used in a semiconductor device, and more particularly, to an address buffer only having (N/2) stages for processing N additive latency.
2. Description of the Related Art
In order to increase a bandwidth, high speed semiconductor memory device use a scheme for artificially delaying data during a data write operation or a data read operation. This structure is referred to as additive latency.
FIG. 1 is a timing diagram for explaining the concept of an additive latency. FIG. 2 is a circuit diagram of a conventional address buffer used in semiconductor devices having N additive latency. Referring to FIG. 2, N flip-flops 210_1, 210_2, . . . , and 210_n are connected serial to one another, and each of the flip-flops 210_1, 210_2, . . . , and 210_n sequentially latches an external address ADD in response to a clock signal CLK.
Referring to FIGS. 1 and 2, when a posted CAS read (PCR) command is input, reading of actual data in a high speed semiconductor memory device using additive latency is performed after additive latency (AL=2) and column address strobe (CAS) latency (CL=3). In this case, an address is delayed by total latency (RL=5) and output.
Thus, when there is N additive latency in a semiconductor device, an address buffer including N-stage flip-flops shown in FIG. 2 is needed. Each of the flip-flop 210_1, 210_2, . . . , and 210_n stores an address of a PCR command that is consecutively input.
However, an interval DAL (delay address latency) between PCR commands of a general specification is over 2 clock cycle (2CK). Thus, there is no case where an address is stored in all stages of an address buffer 200. That is, when the maximum address is stored in the address buffer 200, only (N/2) stages are needed, and thus, the other N/2 stages are not needed.
However, when stages of the address buffer shown in FIG. 2 are reduced to (N/2), N additive latency cannot be secured. Thus, a circuit does not operate normally.